LTC3370 datasheet(19/44 Pages) LINER

19 / 44 page

LTC3372

Rev. A

For more information www.analog.com

Output Overvoltage Protection

Overvoltage comparators guard against transient over-

shoots as well as other more serious conditions that may

overvoltage the output.

When the VOUT/EXTVCC pin voltage rises by more than

7.5%aboveitsregulationsetpoint,thetoppowerMOSFET

gate (TG) is turned off and the bottom power MOSFET gate

(BG)isturnedonuntiltheovervoltageconditioniscleared.

The SENSE– pin functions as the output voltage sense pin

for a secondary +15% overvoltage protection in addition

to the +7.5% overvoltage protection at VOUT/EXTVCC pin.

When voltage at this pin is over 15% higher than the

regulated output voltage set point, the HV controller will

turn TG off and BG on. This provides an additional layer of

protection when point-of-load (POL) regulation is desired.

Power Good Indicator (PGOOD) Pin

The PGOOD pin is connected to the open drain of an

internal N-channel MOSFET. The MOSFET turns on and

pulls the PGOOD pin low when the VOUT/EXTVCC voltage

is outside of the ±7.5% window around the regulated

level. The PGOOD pin is also pulled low when the RUN

pin is low (shut down). When the VOUT/EXTVCC voltage is

within the ±7.5% window, the MOSFET is turned off and

the pin is allowed to be pulled up by an external resistor

to a source no greater than 6V.

Foldback Current Limit

When the output voltage falls to less than 70% of its nominal

level,foldbackcurrentlimitingisactivated.Foldbackprogres-

sively lowers the peak current limit as the output drops in a

sustainedovercurrentorshort-circuitcondition.Foldbackcur-

rent limiting is disabled during the soft-start interval (as long

as the VFB voltage is keeping up with the TRACK/SS voltage).

Light Load Current Operation

The HV buck controller can be enabled to enter one of

the three modes at light load current: (a) high efficiency

Burst Mode, (b) forced continuous conduction mode, or

The LTC3372’s PLL/MODE pin selects the light load

operation modes for both the HV controller and LV

buck regulators. To select Burst Mode operation, tie the

PLL/MODE pin to SGND. To select forced continuous

mode operation, tie the PLL/MODE pin to INTVCC. When

PLL/MODE pin is connected to an external clock, both HV

controller and the LV buck regulators are synchronized to

the external clock in forced continuous mode operation.

To select pulse-skipping mode for the HV controller, tie the

PLL/MODE pin to a DC voltage greater than 1.2V but less

than INTVCC – 3.3V. The LV buck regulators will operate

in Burst Mode operation.

When the controller is enabled for Burst Mode operation, the

minimum peak current in the inductor is set to approximately

25% of the maximum sense voltage even though the voltage

on the ITH pin indicates a lower value. If the average inductor

current is higher than the load current, the error amplifier,

EA, will decrease the voltage on the ITH pin. When the ITH

voltage drops below 0.425V, the internal sleep signal goes

high (enabling sleep mode) and both external MOSFETs are

turned off. The ITH pin is then disconnected from the output

of the EA and parked at 0.450V.

In sleep, much of the internal circuitry is turned off, re-

ducing the quiescent currents that the controllers draws.

The load current is supplied by the output capacitor. As

the output voltage decreases, the EA’s output begins to

rise. When the output voltage drops enough, the ITH pin

is reconnected to the output of the EA, the sleep signal

goes low, and the controller resumes normal operation

by turning on the top external MOSFET on the next cycle

of the internal oscillator.

When the controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

current comparator, IREV, turns off the bottom external

MOSFET just before the inductor current reaches zero,

preventing it from reversing and going negative. Thus, the

controller operates in discontinuous operation.

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by

the voltage on the ITH pin, just as in normal operation.

In this mode, the efficiency at light loads is lower than in

OPERATION

LTC3370 データシート(PDF) 19 Page - Linear Technology

LTC3370 データシート(HTML) 19 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

データシートダウンロード