GD25Q127CSJS datasheet(18/79 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q127C

7.1.

Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)

bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status

goes low  sending the Write Enable command  CS# goes high.

Figure3. Write Enable Sequence Diagram

7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:

CS# goes lowSending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-

up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,

Erase/Program Security Registers and Reset commands.

Figure4. Write Disable Sequence Diagram

7.3. Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the

system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or

affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command

must be issued prior to a Write Status Register command, and any other commands cannot be inserted between them.

Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command

will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status

Command

06H

CS#

SCLK

High-Z

Command

04H

CS#

SCLK

High-Z

GD25Q127CSJS データシート(PDF) 18 Page - GigaDevice Semiconductor (Beijing) Inc.