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GD25VQ40CSIG データシート(PDF) 27 Page - GigaDevice Semiconductor (Beijing) Inc.

部品番号 GD25VQ40CSIG
部品情報  Uniform Sector Dual and Quad Serial Flash
PDF  56 Pages
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メーカー  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
ホームページ  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25VQ40CSIG データシート(HTML) 27 Page - GigaDevice Semiconductor (Beijing) Inc.

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Uniform Sector
Dual and Quad Serial Flash
GD25VQ40C
27
Figure19.Quad Page Program Sequence Diagram
7.16.
Sector Erase (SE) (20H)
The Sector Erase (SE) command is used to erase all the data of the chosen sector. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered
by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-byte address on SI 
CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed.
Command
0
1
2
3
4
5
6
7
32H
CS#
SCLK
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
32 33 34 35
4
0
MSB
36 37 38 39
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
Byte1 Byte2
CS#
SCLK
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
42 43 44 45
41
46 47
40
50 51 52 53
49
54 55
48
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
Byte11
4
0
5
1
6
2
7
3
Byte12
4
0
5
1
6
2
7
3
Byte253
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
Byte256



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