USB2227 datasheet(16/26 Pages) SMSC

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4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs

Datasheet

Revision 1.77 (06-13-05)

SMSC USB2227/USB2228

DATASHEET

Card Insertion

MS_INS

IPU

This pin is the card detection signal from the MS device

to indicate, if the device is inserted.

This pin has an internally controlled weak pull-up

resistor.

System CLK

MS_SCLK

This pin is an output clock signal to the MS device.

The clock frequency is software configurable.

SD INTERFACE

Data3-0

SD_DAT[3:0]

I/O8PU

These are bi-directional data signals.

These pins have internally controlled weak pull-up

resistors.

SD Clock

SD_CLK

This is an output clock signal to SD/MMC device.

The clock frequency is software configurable.

SD Command

SD_CMD

I/O8PU

This is a bi-directional signal that connects to the CMD

signal of SD/MMC device.

This pin has an internally controlled weak pull-up

resistor.

Write Protected

SD_nWP

IPD

This pin is an input signal with an internal weak pull-

down.

This pin has an internally controlled weak pull-down

resistor.

USB INTERFACE

USB Bus Data

USBDM

USBDP

IO-U

These pins connect to the USB bus data signals.

USB Transceiver

Bias

RBIAS

A 12.0k

Ω, ± 1.0% resistor is attached from VSSA to this

pin, in order to set the transceiver’s internal bias

currents.

Analog Test

ATEST

AIO

This signal is used for testing the analog section of the

chip and should be connected to VDDA33 for normal

operation.

1.8v PLL Power

VDD18PLL

1.8v Power for the PLL

PLL Ground

Reference

VSSPLL

Ground Reference for 1.8v PLL power

3.3v Analog Power

VDDA33

3.3v Analog Power

Analog Ground

Reference

VSSA

Analog Ground Reference for 3.3v Analog Power.

Crystal

Input/External Clock

Input

XTAL1/

CLKIN

ICLKx

24Mhz Crystal or external clock input.

This pin can be connected to one terminal of the crystal

or can be connected to an external 24Mhz clock when

a crystal is not used.

Note:

The ‘MA[2:0] pins will be sampled while

nRESET is asserted, and the value will be

latched upon nRESET negation. This will

determine the clock source and value.

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

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