ADRF5721

Data Sheet

Rev. 0 | Page 12 of 17

SERIAL MODE INTERFACE

The ADRF5721 supports a 3-wire SPI: serial data input

(SERIN), clock (CLK), and latch enable (LE). The serial control

interface is activated when PS is set to high.

The ADRF5721 attenuation state is controlled by Bits[D5:D2].

Bit D0 and Bit D1 are don't care bits but must be input.

Therefore, at least a 6-bit SERIN must be used to control the

attenuation states. If using an 8-bit word to control the state of

the attenuator, Bits[D7:D6] and Bits[D1:D0] are don’t care bits.

It does not matter if these bits are held low or high. Refer to Table 7

and Figure 24 for additional information.

In serial mode, the SERIN data is clocked most significant bit

(MSB) first on the rising CLK edges into the shift register. Then,

LE must be toggled high to latch the new attenuation state into

the device. LE must be set to low to clock new SERIN data into

the shift register as CLK is masked to prevent the attenuator

value from changing if LE is kept high. See Figure 24 in

conjunction with Table 2 and Table 7.

USING SEROUT

The ADRF5721 also features a serial data output, SEROUT.

SEROUT outputs the serial input data at the eighth clock cycle,

and can control a cascaded attenuator using a single SPI bus.

Figure 25 shows the serial output timing diagram.

When using the attenuator in a daisy-chain operation, 8-bit

SERIN data must be used due to the 8-clock cycle delay

between SERIN and SEROUT.

It is optional to use a 1 kΩ resistor between SEROUT on the

first attenuator and SERIN of the next attenuator to filter the

signal (see Figure 23).

Figure 23. Using a Resistor on SEROUT

Figure 24. Serial Control Timing Diagram

Figure 25. Serial Output Timing Diagram

4

3

2

1

0

0

200

100

300

400

500

150

50

250

350

450

TIME (ns)

WITHOUT 1kΩ

WITH 1kΩ

X

X

SERIN

CLK

LE

PS

D7

D6

D5

D4

D3

D2

D1

D0

X

X

D[7:0]

NEXT WORD

[FIRST IN]

OPTIONAL

[LAST IN]

DON’T CARE

DON’T

CARE

LSB

OPTIONAL

MSB

X

SERIN

CLK

LE

SEROUT

PS

D5

X

D4

D3

D2

D1

D0

D5

X

D4

D3

D2

D1

D0

X

X

1

2

3

4

5

6

7

8

9

10

11

12

13

14