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ADRF5730BCCZN-R7 データシート(PDF) 15 Page - Analog Devices

部品番号 ADRF5730BCCZN-R7
部品情報  Silicon Digital Attenuator
PDF  19 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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ADRF5730BCCZN-R7 データシート(HTML) 15 Page - Analog Devices

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Data Sheet
ADRF5730
Rev. 0 | Page 15 of 19
Figure 34. Serial Control Timing Diagram
Figure 35. Serial Output Timing Diagram
PARALLEL MODE INTERFACE
The ADRF5730 has six digital control inputs, D0 (LSB) to D5
(MSB), to select the desired attenuation state in parallel mode, as
shown in Table 7. The parallel control interface is activated when
PS is set to low.
There are two modes of parallel operation: direct parallel and
latched parallel.
Direct Parallel Mode
To enable direct parallel mode, the LE pin must be kept high.
The attenuation state is changed by the control voltage inputs
(D0 to D5) directly. This mode is ideal for manual control of the
attenuator.
Latched Parallel Mode
To enable latched parallel mode, the LE pin must be kept low
when changing the control voltage inputs (D0 to D5) to set the
attenuation state. When the desired state is set, LE must be
toggled high to transfer the 6-bit data to the bypass switches of
the attenuator array, and then toggled low to latch the change
into the device until the next desired attenuation change (see
Figure 36 in conjunction with Table 2).
Figure 36. Latched Parallel Mode Timing Diagram
X
X
SERIN
CLK
LE
PS
D7
D6
D5
D4
D3
D2
D1
D0
X
X
D[7:0]
NEXT WORD
[FIRST IN]
OPTIONAL
[LAST IN]
LSB
OPTIONAL
MSB
tCS
tCH
tSCK
tLN
tCKN
tLES
tLEW
X
SERIN
CLK
LE
SEROUT
PS
D5
X
D4
D3
D2
D1
D0
D5
X
D4
D3
D2
D1
D0
X
X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tCO
D5 TO D0
PS
LE
tPS
tPH
tLEW
X
X
X



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