LM2502 datasheet(20/27 Pages) NSC

20 / 27 page

Functional Description (Continued)

TABLE 8. READ — Intel µP Interface Parameters

No.

Parameter

Min

Typ

Max

Units

MasterIN

Set Up Time (A/D, RD*) and Data On Time

MasterIN

Hold Time (A/D, RD*) and Data Off Time

Master

Master Latency

MC Cycles

Slave

Slave Latency

MC Cycles

Slave

Read* Delay

MC Cycles

Slave

Read Low Pulse Width

MC Cycles

Slave

Data Set Up Time

Slave

Data Hold Time

Slave

Slave Read Latency

MC Cycles

T10

Master

MST Read Latency and INTR Delay

MC Cycles

T11

Master

Data Delay

18.6

T12

MasterOUT

Data Valid after Strobe

T13

MasterOUT

RD* active pulse width

T14

MasterOUT

INTR De-assert

MC Cycles

T15

MasterOUT

Recovery Time

T16

MasterOUT

INTR Response, (Note 5)

MC Cycles

LM2502 Features and Operation

POWER SUPPLIES

The V

DDcore and VDDA (MPL and PLL) must be connected to

the same potential between 2.9V and 3.3V. V

DDIO powers

the logic interface and may be powered between 1.7 and

3.3V to be compatible with a wide range of host and target

devices. V

DDIO should not be powered up without VDDcore/

DDA applied as VDDcore biases the IO ring. During power

up, all rails should power up at the same time, or V

DDcore/

DDA should lead.

POWER DOWN/OFF

The Master and the Slave provide a PD* pin to save power

when the link is not needed. A Low on this pin will power

down the entire device and turn off the line current to MD0,

MD1, and MC.

During power up, the PD* inputs should be held LOW and

released once power is stable and within specification. The

Slave PD* may be released first or at the same time as the

Master’s PD* pin. CLK (Master) should be applied prior to

releasing PD*. If the Powerdown state is not required, the

PD* pins maybe connected to V

DDIO, however VDDIO should

power up smooth through the logic threshold region.

In Powerdown (PD* = GND) the following outputs are driven

to:

Master:

INTR = L

Slave depends on mode configuration - see Table 9.

TABLE 9. SLV Output in Powerdown

SLV

i80

SLV

m68

Data[n]

CLK

CS1*

CS2*

MF0

MF1

BYPASS RECOMMENDATIONS

Bypass capacitors should be placed near the power supply

pins of the device. Use high frequency ceramic (surface

mount recommended) 0.1 µF capacitors. A 2.2 to 4.7 µF

Tantalum capacitor is recommended near the Master (SER)

DDA pin for PLL bypass. Connect bypass capacitors with

wide traces and use dual or larger via to reduce resistance

and inductance of the feeds. Utilizing a thin spacing between

power and ground planes will provide good high frequency

bypass above the frequency range where most typical sur-

face mount capacitors are less effective. To gain the maxi-

mum benefit from this, low inductance feed points are impor-

tant. Also, adjacent signal layers can be filled to create

additional capacitance. Minimize loops in the ground returns

also for improved signal fidelity and lowest emissions.

UN-USED/OPEN PINS

Unused inputs must be tied to the proper input level — do not

float them. Unused outputs should be left open to minimize

power dissipation.

PHASE-LOCKED LOOP

When the LM2502 is configured as a Master, a PLL is

enabled to generate the serial link clock. The Phase-locked

loop system generates the serial data clock at several mul-

tiples of the input clock. The PLL operates with an input clock

LM2502 データシート(PDF) 20 Page - National Semiconductor (TI)

LM2502 データシート(HTML) 20 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

データシートダウンロード

リンク URL

LM2502 データシート(PDF) 20 Page - National Semiconductor (TI)

LM2502 データシート(HTML) 20 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

データシート ダウンロード

リンク URL

データシートダウンロード