LM2502SQ datasheet(13/27 Pages) NSC

13 / 27 page

Functional Description (Continued)

fourth section the MD lines are again turned around, such

that the Master becomes the transmitter and the Slave be-

comes the receiver. The Slave drives the MD lines Low for 1

bit width and then turns off. The MD lines are off momentarily

to avoid driver contention. The Master then drives the MD

line Low for 1 bit time and then idles the bus until the next

transaction is sent.

During a READ transaction (Double Read access on the

Master), other MPL transactions are not allowed until the

current READ dual cycle is completed.

To account for the latency through the MPL link, a dual

READ operation is required by the host. The first read re-

turns invalid data (all Low). Once data has returned to the

Master LM2502, the INTR signal is asserted to inform the

host to initiate a second read operation. When the Master

LM2502 sees the Read signal/CS* combination, it will de-

assert the INTR signal and Valid data is presented.

Figure 11 illustrates a m68 mode WRITE followed by a

READ operation (Slave output to Display). At the end of the

WRITE operation the SLAVE outputs are turned off. The

SLAVE latches in the READ data on the rising edge of the

CS* signal as shown. The Display should disable its outputs

prior to the next operation to avoid any bus contention.

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FIGURE 10. READ_Data and TA”

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FIGURE 11. Slave WRITE and Slave READ m68 mode Operation

LM2502SQ データシート(PDF) 13 Page - National Semiconductor (TI)