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CDC305DR データシート(PDF) 3 Page - Texas Instruments

部品番号 CDC305DR
部品情報  OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
PDF  7 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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CDC305DR データシート(HTML) 3 Page - Texas Instruments

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CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
IOH
High-level output current
–24
mA
IOL
Low-level output current
48
mA
TA
Operating free-air temperature
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
VIK
VCC = 4.5 V,
II = – 18 mA
– 1.2
V
VOH
VCC = 4.5 V to 5.5 V,
IOH = – 2 mA
VCC –2
V
VOH
VCC = 4.5 V,
IOH = – 24 mA
2
2.8
V
VOL
VCC = 4.5 V,
IOL = 48 mA
0.3
0.5
V
II
VCC = 5.5 V,
VI = 7 V
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
µA
IIL
VCC = 5.5 V,
VI = 0.4 V
– 0.5
mA
IO‡
VCC = 5.5 V,
VO = 2.25 V
–50
– 150
mA
ICC
VCC = 5.5 V,
See Note 2
40
70
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 2: ICC is measured with CLK and PRE grounded, then with CLK and CLR grounded.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
fclock
Clock frequency
0
80
MHz
CLR or PRE low
5
tw
Pulse duration
CLK high
4
ns
CLK low
6
tsu
Setup time before CLK
CLR or PRE inactive
6
ns



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