データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

V62/12615-01XE-R データシート(PDF) 20 Page - Texas Instruments

Click here to check the latest version.
部品番号 V62/12615-01XE-R
部品情報  DP83848-EP PHYTER??Military Temperature Single Port 10/100 Mbps Ethernet Physical Layer Transceiver
PDF  98 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

V62/12615-01XE-R データシート(HTML) 20 Page - Texas Instruments

Back Button V62/12615-01XE-R Datasheet HTML 16Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 17Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 18Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 19Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 20Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 21Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 22Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 23Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 24Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 98 page
background image
(T/R)
IDLE
DATA
PMD input pair
CRS
T2.10.1
(J/K)
IDLE
DATA
PMD input pair
CRS
RXD[3:0]
RX_DV
RX_ER
T2.9.1
T2.9.2
20
DP83848-EP
SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: DP83848-EP
Specifications
Copyright © 2012–2019, Texas Instruments Incorporated
(1)
Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(2)
1 bit time = 10 ns in 100-Mbps mode.
(3)
PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
4.7.9
100BASE-TX Receive Packet Latency Timing
PARAMETER
DESCRIPTION(1)
NOTES(2) (3)
MIN
TYP
MAX
UNIT
T2.9.1
Carrier sense ON delay
100-Mbps Normal mode
20
bits
T2.9.2
Receive data latency
100-Mbps Normal mode
24
bits
(1)
Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
(2)
1 bit time = 10 ns in 100-Mbps mode.
Figure 4-10. 100BASE-TX Receive Packet Latency Timing
4.7.10 100BASE-TX Receive Packet Deassertion Timing
PARAMETER
DESCRIPTION
NOTES(1) (2)
MIN
TYP
MAX
UNIT
T2.10.1
Carrier sense OFF delay
100-Mbps Normal mode
24
bits
Figure 4-11. 100BASE-TX Receive Packet Deassertion Timing



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com