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VSC9187 データシート(PDF) 2 Page - Vitesse Semiconductor Corporation |
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VSC9187 データシート(HTML) 2 Page - Vitesse Semiconductor Corporation |
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2 / 2 page ![]() Your Partner for Success. For more information on Vitesse Products visit the Vitesse web site at www.vitesse.com or contact Vitesse Sales at (800) VITESSE or sales@vitesse.com ©2002 Vitesse Semiconductor Corporation 741 Calle Plano Camarillo, CA 93012, USA Tel: +1 805.388.3700 Fax: +1 805.987.5896 www.vitesse.com The VSC9187 is a VT1.5 Time Slot Interchange (TSI) Device. It provides a fully non blocking cross connect for 3024 VT1.5's that are all frequency, phase and column aligned in addition to a pre- grooming 2:1 UPSR selection. The device receives 9 x 622 Mb/s STS-12 working and protection backplane inputs and performs all necessary functions to retime and align these signals from the backplane. VT1.5 tributaries are then pre- selected with a hardware 2:1 UPSR switch from the working GENERAL DESCRIPTION: VSC9187 Bromley - 3045 x 3045 VT1.5 TSI Switch Fabric and protection timeslot with programmable holdover and pre- hold switch timers. The results of the 2:1 hardware selection are then made available to an internal 3024x3024 VT1.5 non- blocking grooming switch, allowing a 5G UPSR ring to be terminated. Alternatively, the 9 protection STS-12 backplane inputs can remain unused and the VSC9188 can act as a 5G VT1.5 switch. Output STS-1 delay management following the crossconnect allows the VSC9187 to be used in subtended switch applications with large scale STS-1 crossconnects such as the VSC9182 40Gb/s STS-1 TSI. VSC9187 VSC9187 BLOCK DIAGRAM: LEG_DI_S[5:0] LEG_RCLK_S LEG_RSYN_S [7:0] [8:0] LASB [8] TDM MUX 9 x 622Mb/s STS-12 Serial Backplane Inputs (Service) STS_DI_[8:0] MUX Low-Order Alarm Status Byte (LASB) Inserted by VSC9188 (contains VTI.5 PM summary) LEG_DI_P[5:0] LEG_RCLK_P LEG_RSYN_P [16:9] [17:9] LASB [17] TDM MUX 9 x 622Mb/s STS-12 Serial Backplane Inputs (Protection) [8:0] [8:0] STS_DI_[17:9] JTAG Interface System Interface and PLL HS-CLK LS-CLK SYNC M-SYNC CPU Interface MUX LEG_DO_S[5:0] LEG_TCLK_S LEG_TSYN_S STS_DO_[8:0] LEG_DO_P[5:0] LEG_TCLK_P LEG_TSYN_P STS_DO_[17:9] TDM DEMUX 9 x 622Mb/s STS-12 Serial Backplane Inputs (Service) TDM DEMUX 9 x 622Mb/s STS-12 Serial Backplane Outputs (Protection) |
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