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STR720RBQ6 データシート(PDF) 87 Page - STMicroelectronics |
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STR720RBQ6 データシート(HTML) 87 Page - STMicroelectronics |
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87 / 401 page  STR720 - DMA CONTROLLER (DMAC) 87/401 Destination base address high X (DMADestHiX) (X=2,3) Address Offset: 8Ch - CCh Reset value: 0000h DMADestHiX contains the high base address for stream X destination DMA buffer. Bit 15:0 = DMADestHiX[15:0] Maximum count register X (DMAMaxX) (X=2,3) Address Offset: 90h - D0h Reset value: 0000h This register is programmed with stream X maximum data unit count, defining the buffer size. The data unit is equal to the DMA data with (byte, half-word or word) configured for the source side, if Dir bit of DMACtrlX register is 0, or for the destination side, if Dir bit of DMACtrlX register is 1. Upon enabling DMA Controller, the content of the Maximum Count Register is loaded in the Terminal Count Register. Bit 15:0 = DMAMax0[15:0] 15 14 13 12 11 10 9 8 765432 1 0 DMADestHiX rw 15 14 13 12 11 10 9 8 765432 1 0 DMAMaxX rw 1 |
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