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TPS16632RGER データシート(PDF) 16 Page - Texas Instruments

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部品番号 TPS16632RGER
部品情報  TPS1663x 60-V, 6-A eFuse with Adjustable Output Power Limiting
PDF  43 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

TPS16632RGER データシート(HTML) 16 Page - Texas Instruments

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R1
R2
R3
IN
UVLO
OVP
V(IN)
+
UVLOb
+
OVP
1.2 V
1.12 V
1.2 V
1.12 V
GND
P_IN
VIN
VOUT
PGOOD
IIN
16
TPS1663
SLVSET9D – SEPTEMBER 2018 – REVISED AUGUST 2019
www.ti.com
Product Folder Links: TPS1663
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Feature Description (continued)
CdVdT = Open
COUT = 15 mF
RILIM = 4.02 kΩ
Figure 16. Thermal Regulation Loop Response During Power up with Large Capacitive Load
9.3.2 Undervoltage Lockout (UVLO)
The TPS1663x devices feature an accurate ± 2% adjustable undervoltage lockout functionality. When the voltage
at UVLO pin falls below V(UVLOF) during input undervoltage fault, the internal FET quickly turns off and FLT is
asserted. The UVLO comparator has a hysteresis of 78 mV (typical). To set the input UVLO threshold, connect a
resistor divider network from IN supply to UVLO terminal to GND as shown in Figure 17. If the Under-Voltage
Lock-Out function is not needed, the UVLO terminal must be connected to the IN terminal. UVLO terminal must
not be left floating.
Figure 17. UVLO and OVP Thresholds Set by R1 , R2 and R3



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