SSD1306Z datasheet(21/65 Pages) ETC2

部品番号	SSD1306Z

部品情報	128 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller

PDF	65 Pages

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メーカー	ETC2 [List of Unclassifed Manufacturers]

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21 / 65 page

SSD1306

Rev 1.1

P 21/59

Apr 2008

Solomon Systech

Figure 8-8 : Definition of the Start and Stop Condition

Figure 8-9 : Definition of the acknowledgement condition

Please be noted that the transmission of the data bit has some limitations.

1. The data bit, which is transmitted during each SCL pulse, must keep at a stable state within the “HIGH”

period of the clock pulse. Please refer to the Figure 8-10 for graphical representations. Except in start or

stop conditions, the data line can be switched only when the SCL is LOW.

2. Both the data line (SDA) and the clock line (SCL) should be pulled up by external resistors.

Figure 8-10 : Definition of the data transfer condition

SDA

SCL

Data line is

stable

Change

of data

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

START

Condition

Clock pulse for acknowledgement

Non-acknowledge

Acknowledge

START condition

SDA

SCL

STOP condition

SDA

SCL

tHSTART

tSSTOP

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