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ICS93776 データシート(PDF) 2 Page - Integrated Circuit Systems

部品番号 ICS93776
部品情報  Low Cost DDR Phase Lock Loop Zero Delay Buffer
PDF  8 Pages
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メーカー  ICST [Integrated Circuit Systems]
ホームページ  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS93776 データシート(HTML) 2 Page - Integrated Circuit Systems

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ICS93776
0793A—03/08/05
Pin Descriptions
PIN #
PIN NAME
PIN TYPE DESCRIPTION
1
DDRC0
OUT
"Complementary" Clock of differential pair output.
2
DDRT0
OUT
"True" Clock of differential pair output.
3
VDD
PWR
Power supply, nominal 2.5V
4
DDRT1
OUT
"True" Clock of differential pair output.
5
DDRC1
OUT
"Complementary" Clock of differential pair output.
6
GND
PWR
Ground pin.
7
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
8
CLK_INT
IN
"True" reference clock input.
9
CLK_INC
IN
"Complementary" reference clock input.
10
VDDA
PWR
2.5V power for the PLL core.
11
GND
PWR
Ground pin.
12
VDD
PWR
Power supply, nominal 2.5V
13
DDRT2
OUT
"True" Clock of differential pair output.
14
DDRC2
OUT
"Complementary" Clock of differential pair output.
15
GND
PWR
Ground pin.
16
DDRC3
OUT
"Complementary" Clock of differential pair output.
17
DDRT3
OUT
"True" Clock of differential pair output.
18
FB_OUTC
OUT
Complement single-ended feedback output, dedicated
external feedback. It switches at the same frequency
as other DDR outputs, This output must be connect to
FB_INC.
19
FB_OUTT
OUT
True single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other
DDR outputs, This output must be connect to FB_INT.
20
FB_INT
IN
True single-ended feedback input, provides feedback
signal to internal PLL for synchronization with
CLK_INT to eliminate phase error.
21
FB_INC
IN
Complement single-ended feedback input, provides
feedback signal to internal PLL for synchronization
with CLK_INT to eliminate phase error.
22
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
23
VDD
PWR
Power supply, nominal 2.5V
24
DDRT4
OUT
"True" Clock of differential pair output.
25
DDRC4
OUT
"Complementary" Clock of differential pair output.
26
DDRT5
OUT
"True" Clock of differential pair output.
27
DDRC5
OUT
"Complementary" Clock of differential pair output.
28
GND
PWR
Ground pin.



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