8

CDCDB2000

SNAS787 – NOVEMBER 2019

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Copyright © 2019, Texas Instruments Incorporated

Electrical Characteristics (continued)

VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

Voltage swing includes overshoot.

(2)

Not tested in production. Ensured by design and characterization.

(3)

Measured into DC test load.

(4)

rising.

(5)

Measured from rising edge of CLK_IN to any CKx output.

IO supply current per output

All-outputs disabled

20

mA

All-outputs active, 100MHz

200

Power down mode. CKPWRGD_PD# = 0

8

CLOCK INPUT

Input frequency

50

100

250

MHz

Input voltage swing

Differential voltage between CLKIN_P and

200

2300

peak

dV/dt

Input voltage edge rate

20% - 80% of input swing

0.7

V/ns

140

mV

Input duty cycle

40

60

%

Differential capacitance between CLKIN_P

and CLKIN_N pins

2.2

pF

CLOCK OUTPUT

Output frequency

50

100

250

MHz

Differential capacitance between CKx_P

and CKx_N pins

2.2

pF

Output high voltage

225

270

mV

Output low voltage

10

150

Crossing point voltage

(3) (4)

130

200

(3) (4)

35

Overshoot voltage

(3)

Undershoot voltage

(3)

Differential impedance

81

85

89

ohm

S

Differential impedance

68

85

102

Edge rate

2

20

V/ns

Edge rate matching

20

%

Power good assertion to stable clock

output

CKPWRGD_PD# pin

100 MHz

Measured

when

PWRGD

reaches

0.2V

1.8

ms

Power good assertion to outputs

driven high

CKPWRGD_PD# pin

100 MHz

Measured

when

PWRGD

reaches

0.2V

300

µs

Output enable assertion to stable

clock output

OEx# pin transistions from 1 to 0

10

CLKIN

Periods

Output enable de-assertion to no

clock output

OEx# pin transistions from 0 to 1

10

Power down assertion to no clock

output

CKPWRGD_PD# pin transistions from 1 to

0

3

Duty cycle distortion

–1.0

1.0

%

Propagation delay

3

ns