Nexperia

PRMD13

50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)

12. Package outline

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

SOT1268

- - -

sot1268_po

18-08-23

18-09-11

Note

1. Dimension A is including plating thickness.

0

1 mm

scale

detail X

pin 1

index area

pin 1

index area

(2×)

B

D

A

E

A

e

T

(6×)

e

X

A B

DFN1412-6: plastic thermal enhanced ultra thin small outline package; no leads;

6 terminals; body: 1.4 x 1.2 x 0.47 mm

SOT1268

mm

min

nom

max

1.35 0.43

0.195

0.145

0.245

A

Dimensions (mm are the original dimensions)

b

0.15

D

e

L

0.16

0.10

0.22

T

0.50

0.47

0.44

0.04

0.00

1.45

1.40

0.53

0.25

0.20

1.15

1.25

E

0.32

0.42

0.35

0.5

0.48 1.20 0.37

V

Y

0.1

1

3

6

b

(6×)

4

(2×)

(2×)

L

(6×)

5

2

0.05 0.05

Y

C

C

C

V

Fig. 19. Package outline DFN1412-6 (SOT1268)

PRMD13

All information provided in this document is subject to legal disclaimers.

Product data sheet

14 September 2018

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