CS5378 datasheet(18/86 Pages) CIRRUS

18 / 86 page

CS5378

DS639F1

3. SYSTEM DESIGN WITH CS5378

Figure 9 illustrates a simplified block diagram of

the CS5378 in a single channel measurement sys-

tem.

A differential sensor is connected through the

CS3301/02 differential amplifiers to the CS5371

∆Σ modulator, where analog to digital conversion

occurs. The modulator’s 1-bit output connects to

the CS5378 MDATA input, where the oversam-

pled

∆Σ data is decimated and filtered to 24-bit out-

put samples at a programmed output rate. These

output samples are buffered into an 8-deep data

FIFO and then passed to the system telemetry.

System self tests are performed by connecting the

CS5378 test bit stream (TBS) generator to the

CS4373 test DAC. Analog tests drive differential

signals from the CS4373 test DAC into the multi-

plexed inputs of the CS3301/02 amplifiers or di-

rectly to the differential sensor. Digital loopback

tests internally connect the TBS digital output di-

rectly to the CS5378 modulator input.

3.1 Power Supplies

The system shown in Figure 9 typically operates

from a ±2.5 V or a 5 V analog power supply and a

3.3 V digital power supply. The CS5378 logic core

can be powered from 2.5 V to minimize power con-

sumption, if required.

3.2 Reset Control

System reset is required only for the CS5378 de-

vice, and is a standard active low signal that can be

generated by a power supply monitor or microcon-

troller. Other system devices default to a power-

down state when the CS5378 is reset.

3.3 PLL and Clock Generation

A PLL is included on the CS5378 to generate an in-

ternal

32.768 MHz

master

clock

from

1.024 MHz, 2.048 MHz, or 4.096 MHz standard

clock or manchester encoded input. Clock inputs

for other system devices are driven by clock out-

puts from the CS5378.

Digital Filter

w/ PLL

AMP

Geophone

Hydrophone

Sensor

µController

Configuration

EEPROM

Communication

Interface

CS3301

CS3302

CS5378

System

Telemetry

∆Σ

Modulator

CS5371

∆Σ

Test DAC

CS4373

Figure 9. Single-Channel System Block Diagram

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