CS44210

22

DS539PP1

4.9 Mode Control 2 (address 0Ah)

4.9.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other

internal circuitry. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK require-

ments. Refer to Tables 11, 12, 13, 14, and Section 6.2.

4.9.2 CLOCK DIVIDE (CLKDIV)

Default = 00

Function:

MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to

Tables 11, 12, 13, 14, and Section 6.2.

4.9.3 DOUBLE SPEED MODE (DBS)

Default = 0

0 - Single Speed

1 - Double Speed (DBS)

Function:

Single Speed supports 8kHz to 50 kHz sample rates and Double Speed supports 50 kHz to 96kHz sample

rates. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer

to Tables 11, 12, 13, 14, and Section 6.2.

Note: De-emphasis, ramp control, and treble control are not available in Double Speed Mode.

4.9.4 FREQUENCY SHIFT (FRQSFT)

Default = 00

Function:

MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to

Tables 11, 12, 13, 14, and Section 6.2.

76543

210

MCLKDIV

CLKDV1

CLKDV0

DBS

FRQSFT1

FRQSFT0

DEM1

DEM0

00000

000