AD5258BRMZ10-R71 datasheet(19/24 Pages) AD

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AD5258

Rev. 0 | Page 19 of 24

ESD PROTECTION OF DIGITAL PINS AND

RESISTOR TERMINALS

The AD5258 VDD, VLOGIC, and GND power supplies define the

boundary conditions for proper 3-terminal and digital input

operation. Supply signals present on Terminal A, Terminal B,

and Terminal W that exceed VDD or GND are clamped by the

internal forward biased ESD protection diodes (see Figure 41).

Digital Input SCL and Digital Input SDA are clamped by ESD

protection diodes with respect to VLOGIC and GND as shown in

Figure 42.

GND

VDD

Figure 41. Maximum Terminal Voltages Set by VDD and GND

GND

SCL

SDA

VLOGIC

Figure 42. Maximum Terminal Voltages Set by VLOGIC and GND

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at Terminal A, Terminal B, and Terminal W (see Figure 41), it is

important to power GND/VDD/VLOGIC before applying any

voltage to Terminal A, Terminal B, and Terminal W; otherwise,

the diode is forward biased such that VDD and VLOGIC are

powered unintentionally and may affect the user’s circuit. The

ideal power-up sequence is in the following order: GND, VDD,

VLOGIC, digital inputs, and then VA, VB, VW. The relative order of

powering VA, VB, VW, and the digital inputs is not important as

long as they are powered after GND/VDD/VLOGIC.

LAYOUT AND POWER SUPPLY BYPASSING

It is good practice to employ compact, minimum lead length

layout design. The leads to the inputs should be as direct as

possible with minimum conductor length. Ground paths should

have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies

with quality capacitors for optimum stability. Supply leads to

the device should be bypassed with disc or chip ceramic

capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum

or electrolytic capacitors should also be applied at the supplies

to minimize any transient disturbance and low frequency ripple

(see Figure 43). The digital ground should also be joined

remotely to the analog ground at one point to minimize the

ground bounce.

VDD

GND

VDD

µF

0.1

µF

AD5258

Figure 43. Power Supply Bypassing

MULTIPLE DEVICES ON ONE BUS

The AD5258 has two three-state configurable Address Pins

AD0 and AD1. The state of these two pins is registered upon

power-up and decoded into a corresponding I2C 7-bit address

(see Table 5). This allows up to nine devices on the bus to be

written to, or read from, independently. In the case that the pin

is assigned to be floated, the static voltage will be VLOGIC/2.

EVALUATION BOARD

An evaluation board, along with all necessary software, is

available to program the AD5258 from any PC running

Windows® 98/2000/XP. The graphical user interface, as shown

in Figure 44, is straightforward and easy to use. More detailed

information is available in the user manual that comes with the

board.

Figure 44. AD5258 Evaluation Board Software

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