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AM652X データシート(PDF) 161 Page - Texas Instruments |
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AM652X データシート(HTML) 161 Page - Texas Instruments |
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161 / 277 page  RMII[x]_REFCLK (input) RMII2 RMII3 RMII1 MDIO3 MDIO1 MDIO2 MDIO7 MDIO4 MDIO5 MDIO6 MDIO6 MDIO_CLK MDIO_DATA (input) MDIO_DATA (output) SPRSP08_CPSW2G_MDIO 161 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated Table 5-33. Switching Characteristics Over Recommended Operating Conditions for MDIO Output NO. PARAMETER MIN MAX UNIT MDIO3 tc(MDC) Cycle time, MDIO_CLK 400 ns MDIO4 tw(MDCH) Pulse Duration, MDIO_CLK high 160 ns MDIO5 tw(MDCL) Pulse Duration, MDIO_CLK low 160 ns MDIO6 tt(MDC) Transition time, MDIO_CLK 5 ns MDIO7 td(MDC_MDIO) Delay time, MDIO_CLK low to MDIO_DATA valid -150 150 ns Figure 5-28. CPSW2G MDIO Diagrams Receive and Transmit 5.9.5.2.2 CPSW2G RMII Timings Table 5-34, Table 5-35, Figure 5-29, and Figure 5-30 present timing requirements for CPSW2G RMII receive. Table 5-34. Timing Requirements for RMII[x]_REFCLK - RMII Mode NO. PARAMETER DESCRIPTION MIN TYP MAX UNIT RMII1 tc(REF_CLK) Cycle time, REF_CLK 19.999 20.001 ns RMII2 tw(REF_CLKH) Pulse Duration, REF_CLK High 7 13 ns RMII3 tw(REF_CLKL) Pulse Duration, REF_CLK Low 7 13 ns Figure 5-29. RMII[x]_REFCLK Timing - RMII Mode Table 5-35. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode NO. PARAMETER DESCRIPTION MIN TYP MAX UNIT RMII4 tsu(RXD-REF_CLK) Setup time, RXD[1:0] valid before REF_CLK 4 ns tsu(CRS_DV-REF_CLK) Setup time, CRS_DV valid before REF_CLK 4 ns tsu(RX_ER-REF_CLK) Setup time, RX_ER valid before REF_CLK 4 ns |
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