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AM652X データシート(PDF) 77 Page - Texas Instruments |
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AM652X データシート(HTML) 77 Page - Texas Instruments |
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77 / 277 page  77 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Terminal Configuration and Functions Copyright © 2017–2019, Texas Instruments Incorporated Table 4-27. GPMC0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPMC0_AD8 GPMC Data 8 Input/Output in A/D non-multiplexed mode and additionally Address 9 Output in A/D multiplexed mode IO N23 GPMC0_AD9 GPMC Data 9 Input/Output in A/D non-multiplexed mode and additionally Address 10 Output in A/D multiplexed mode IO M26 GPMC0_AD10 GPMC Data 10 Input/Output in A/D non-multiplexed mode and additionally Address 11 Output in A/D multiplexed mode IO P28 GPMC0_AD11 GPMC Data 11 Input/Output in A/D non-multiplexed mode and additionally Address 12 Output in A/D multiplexed mode IO P27 GPMC0_AD12 GPMC Data 12 Input/Output in A/D non-multiplexed mode and additionally Address 13 Output in A/D multiplexed mode IO N26 GPMC0_AD13 GPMC Data 13 Input/Output in A/D non-multiplexed mode and additionally Address 14 Output in A/D multiplexed mode IO N25 GPMC0_AD14 GPMC Data 14 Input/Output in A/D non-multiplexed mode and additionally Address 15 Output in A/D multiplexed mode IO P24 GPMC0_AD15 GPMC Data 15 Input/Output in A/D non-multiplexed mode and additionally Address 16 Output in A/D multiplexed mode IO R27 GPMC0_BE0n_CLE GPMC Lower-Byte Enable (active low) or Command Latch Enable O T28 GPMC0_BE1n GPMC Upper-Byte Enable (active low) O P23 GPMC0_CSn0 GPMC Chip Select 0 (active low) O R24 GPMC0_CSn1 GPMC Chip Select 1 (active low) O T23 GPMC0_CSn2 GPMC Chip Select 2 (active low) O R25 GPMC0_CSn3 GPMC Chip Select 3 (active low) O T27 GPMC0_WAIT0 GPMC External Indication of Wait I R26 GPMC0_WAIT1 GPMC External Indication of Wait I R23 4.3.12 HyperBus 4.3.12.1 MCU Domain Table 4-28. HYPERBUS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_HYPERBUS0_CK Hyperbus Differential Clock (positive) O V1 MCU_HYPERBUS0_CKn Hyperbus Differential Clock (negative) O U1 MCU_HYPERBUS0_INTn Hyperbus Interrupt (active low) I P2 MCU_HYPERBUS0_RESETn Hyperbus Reset (active low) Output O R5 MCU_HYPERBUS0_RESETOn Hyperbus Reset Status Indicator (active low) from Hyperbus Memory I R1 MCU_HYPERBUS0_RWDS Hyperbus Read-Write Data Strobe IO U2 MCU_HYPERBUS0_WPn Hyperbus Write Protect (Not in use) O N3 MCU_HYPERBUS0_CSn0 Hyperbus Chip Select 0 O R4 MCU_HYPERBUS0_CSn1 Hyperbus Chip Select 1 O N3 MCU_HYPERBUS0_DQ0 Hyperbus Data 0 IO U4 MCU_HYPERBUS0_DQ1 Hyperbus Data 1 IO U5 |
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