AM652X datasheet(257/277 Pages) TI1

257 / 277 page

Device

VDDA_VSYS_MON

SPRSP08_VSYS_MON_01

VSS

30 k

Ω

220 k

Ω

VSYS

(System Power Suplpy)

257

AM6548, AM6528, AM6546

AM6526, AM6527

www.ti.com

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

Submit Documentation Feedback

Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Applications, Implementation, and Layout

The USB0_VBUS and USB1_VBUS pins may be considered to be fail-safe because the external circuit in

Figure 7-4 limits the input current to the actual device pin in a case where VBUS is applied while the

device is powered off.

7.2.4

High Speed Differential Signal Routing Guidance

The High-Speed Interface Layout Guidelines provides guidance for successful routing of the high speed

differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and

spacing limits. TI supports only designs that follow the board design guidelines contained in the

application report.

7.2.5

System Power Supply Monitor Design Guidelines

The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe,

unless implemented with the appropriate resistor voltage divider source. This pin should be sourced with a

resistor voltage divider that receives its power from the system power supply.

The output of the resistor voltage divider is connected to the VDDA_VSYS_MON pin which has a trigger

voltage of 0.5 V ± 5%. The resistor voltage divider should be implemented such that it has a reference

current in the range of 1 µA to 50 µA, output voltage that never exceeds the maximum value defined in

Section 5.1, Absolute Maximums Ratings, and output voltage of 0.54 V when the system supply drops to

its lowest desired operating voltage.

The recommended output voltage of 0.54 V provides 40 mV of margin that includes 5% for tolerance of

the voltage monitor, 1% for tolerance of each resistor, plus 5 mV of potential error introduced by input

leakage current. This value ensures the voltage monitor will never trigger before reaching the expected

trigger voltage.

Figure 7-5 presents an example, when the system power supply voltage is nominally 5 V and the desired

trigger threshold is -10% or 4.5 V.

Figure 7-5. System Supply Monitor Voltage Divider Circuit

In this example the voltage divider ratio should be (4.5 V / 0.54 V) = 8.33 V. This ratio produces a 0.54 V

potential on the VDDA_VSYS_MON pin when the system power supply is 4.5 V. In this case, the voltage

monitor will trigger in the range of 3.88 V to 4.5 V. Precision 1% resistors with similar thermal coefficient

are recommended for implementing the resistor voltage divider.

7.2.6

MMC Design Guidelines

The MMC peripheral on this device contains an integrated SDIO LDO for handling automatic voltage

transitions for SD Interfaces. For details about how to connect the device pins associated with the SDIO

LDO, refer to Figure 7-10 through .

AM652X データシート(PDF) 257 Page - Texas Instruments

AM652X データシート(HTML) 257 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード