 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
ST8500TR データシート(PDF) 5 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST8500TR データシート(HTML) 5 Page - STMicroelectronics |
|
|
5 / 37 page  DocID031029 Rev 3 5/37 ST8500 Device architecture 37 2 Device architecture The ST8500 architecture is composed of the following parts: 1. PLC front-end including digital front-end (DFE) and analog front-end (AFE) 2. Real-time engine: the digital core running the lower layers of the PLC protocol stack and implementing modulation, demodulation and advanced forward error corrections (FEC) algorithms 3. Protocol engine: the digital core running the upper layers of the PLC protocol stack and managing the interface with external microcontrollers. 4. Peripherals, crypto, debug section 5. Clock and reset section 6. Power management section The ST8500 detailed architecture is shown in Figure 2. |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
