where R

approximately 900k

Ω. Since R

R

can be neglected until a value is chosen to set the zero f

f

capacitor, f

ent load currents as shown by the equation, so setting the

zero is not exact. Determine the range of f

pected loads and then set the zero f

mately in the middle. The frequency of this zero is deter-

mined by:

Now R

Check to make sure that the pole f

500Hz range, change each value slightly if needed to ensure

both component values are in the recommended range.

HIGH OUTPUT CAPACITOR ESR COMPENSATION

When using an output capacitor with a high ESR value, or

just to improve the overall phase margin of the control loop,

another pole may be introduced to cancel the zero created

by the ESR. This is accomplished by adding another capaci-

tor, C

parallel with the series combination of R

should be placed at the same frequency as f

zero. The equation for this pole follows:

To ensure this equation is valid, and that C

without negatively impacting the effects of R

must be greater than 10f

CHECKING THE DESIGN

With all the poles and zeros calculated the crossover fre-

quency can be checked as described in the section DC Gain

and Open-loop Gain. The compensation values can be

changed a little more to optimize performance if desired.

This is best done in the lab on a bench, checking the load

step response with different values until the ringing and

overshoot on the output voltage at the edge of the load steps

is minimal. This should produce a stable, high performance

circuit. For improved transient response, higher values of R

C

should be chosen. This will improve the overall bandwidth

which makes the regulator respond more quickly to tran-

sients. If more detail is required, or the most optimum per-

formance is desired, refer to a more in depth discussion of

compensating current mode DC/DC switching regulators.

POWER DISSIPATION

The output power of the LM3224 is limited by its maximum

power dissipation. The maximum power dissipation is deter-

mined by the formula

P

θ

JA

where T

(125˚C), T

θ

mal resistance of the package.

LAYOUT CONSIDERATIONS

The input bypass capacitor C

operating circuit, must be placed close to the IC. This will

reduce copper trace resistance which effects input voltage

ripple of the IC. For additional input voltage filtering, a 100nF

bypass capacitor can be placed in parallel with C

the V

output capacitor, C

IC. Any copper trace connections for the C

increase the series resistance, which directly effects output

voltage ripple. The feedback network, resistors R

R

inductor, to minimize copper trace connections that can in-

ject noise into the system. Trace connections made to the

inductor and schottky diode should be minimized to reduce

power dissipation and increase overall efficiency. For more

detail on switching power supply layout considerations see

Application Note AN-1149: Layout Guidelines for Switching

Power Supplies.

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