580

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

Ordering Information

PART NUMBER

TEMPERATURE RANGE

SCREENING LEVEL

PACKAGE

HCTS191DMSR

Intersil Class S Equivalent

16 Lead SBDIP

HCTS191KMSR

Intersil Class S Equivalent

16 Lead Ceramic Flatpack

HCTS191D/Sample

Sample

16 Lead SBDIP

HCTS191K/Sample

Sample

16 Lead Ceramic Flatpack

HCTS191HMSR

Die

Die

HCTS191MS

Radiation Hardened

Synchronous 4-Bit Up/Down Counter

Pinouts

16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

(SBDIP) MIL-STD-1835 CDIP2-T16

TOP VIEW

16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

(FLATPACK) MIL-STD-1835 CDFP4-F16

TOP VIEW

TRUTH TABLE

FUNCTION

PL

CE

U/D

CP

Count Up

H

L

L

Count Down

H

L

H

Asynchronous Preset

L

X

X

X

No Change

H

H

X

X

H = High Level, L = Low Level, X = Immaterial

= Transition from low to high

NOTE: U/D or CE should be changed only when CLOCK (CP)

is high.

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

Q1

Q0

CE

U/D

Q2

GND

Q3

CP

RC

TC

PL

P2

P0

P1

VCC

P3

2

3

4

5

6

7

8

116

15

14

13

12

11

10

9

Q1

Q0

CE

U/D

Q2

GND

Q3

P1

CP

RC

TC

PL

P2

P0

VCC

P3

Features

• 3 Micron Radiation Hardened CMOS SOS

• Total Dose 200K RAD (Si)

Day (Typ)

• Latch-Up Free Under Any Conditions

• Fanout (Over Temperature Range)

- Standard Outputs - 10 LSTTL Loads

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• LSTTL Input Compatibility

- VIL = 0.8V Max

- VIH = VCC/2 Min

• Input Current Levels Ii

≤ 5µA @ VOL, VOH

Description

The Intersil HCTS191MS is a Radiation Hardened asynchro-

nously presettable 4 bit binary up/down synchronous counter.

Presetting the counter to the number on the preset data inputs

(P0 - P3) is accomplished by a low asynchronous parallel load

input (PL). Counting occurs when PL is high, Count Enable (CE)

is low, and the Up/Down (U/D) input is either low for up-counting

or high for down-counting. The counter is incremented or decre-

mented synchronously with the low-to-high transition of the clock.

When an overflow or underflow of the counter occurs, the

Terminal Count output (TC), which is low during counting, goes

high and remains high for one clock cycle. This output can be

used for look-ahead carry in high speed cascading. The TC

output also initiates the Ripple Clock output (RC) which, normally

high, goes low and remains low for the low-level portion of the

clock pulse. These counter can be cascaded using the Ripple

Carry output.

The HCTS191MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of

radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCTS191MS is supplied in a 16 lead Ceramic flatpack

(K suffix) or a SBDIP Package (D suffix).

September 1995

Spec Number

518621

File Number

2250.2