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XRT7250 データシート(PDF) 40 Page - Exar Corporation |
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XRT7250 データシート(HTML) 40 Page - Exar Corporation |
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40 / 463 page  áç áç áç áç DS3/E3 FRAMER IC XRT7250 REV. 1.1.1 21 t27 TxInClk clock (falling) edge to “TxOHIns” hold-time 100 50 12 ns ns ns DS3 Applications E3, ITU-T G.832 Applications E3, ITU-T G.751 Applications t28 “TXOHIns” to “TxInClk” (falling edge) set-up Time 920 140 20 ns ns ns DS3 Applications E3, ITU-T G.832 Applications E3, ITU-T G.751 Applications t29 TxInClk clock (falling) edge to “TxOHIns” hold-time 100 50 12 ns ns ns DS3 Applications E3, ITU-T G.832 Applications E3, ITU-T G.751 Applications t29A “TxOHEnable” to “TxOHIns/TxOH” Delay 1ns Transmit LIU Interface Timing (see Figure 7 and Figure 8) t30 Rising edge of "TxLineClk" to rising edge of "TxPOS" or "TxNEG" output signal. (Framer is configured to output data on "TxPOS" and "TxNEG" on rising edge of "TxLineClk" 12.0 ns t31 Falling edge of "TxLineClk" to rising edge of "TxPOS" or "TxNEG" (Framer is configured to output data via "TxPOS" and "TxNEG" on falling edge of "TxLineClk") 14 ns fTxLineClk Period of TxLineClk clock signal 44.736 MHz DS3 Applications fTxLineClk Period of TxLineClk clock signal 34.368 Mhz E3 Applications t32 Period of TxLineClk 22.36 ns DS3 Applications t32 Period of TxLineClk 29.10 ns E3 Applications Receive LIU Interface Timing (see Figure 9 and Figure 10) t38 "RxPOS" or "RxNEG" set-up time to rising edge of "RxLineClk". (Framer is configured to sample data on "RxPOS" and "RxNEG" input pins, on the rising edge of "RxLi- neClk") 3ns t39 "RxPOS" or "RxNEG" hold time, from rising edge of "RxLineClk" (Framer is configured to sample data on "RxPOS" and "RxNEG" input pins, on the rising edge of "RxLi- neClk") 5ns AC ELECTRICAL CHARACTERISTICS (CONT.) Test Conditions: TA = 25(C, VCC = 5.0V + 5% unless otherwise specified SYMBOL PARAMETER MIN.TYP.MAX.UNITS CONDITIONS |
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