LPC55S6X datasheet(91/128 Pages) NXP

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LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

91 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

11.11 High-Speed SPI interface (Flexcomm Interface 8)

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for SPI master

mode (transmit/receive) and for SPI slave mode (transmit/receive) is 50 Mbit/s.

[1]

Based on simulated values. Not tested in production.

Table 33.

SPI dynamic characteristics[1]

Tamb = 40 C to 105 C; VDD = 1.8 V to 3.6 V; CL = 10 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

fast mode for all pins;. Parameters sampled at the 50% level of the rising or falling edge.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SPI master

tDS

data set-up time

tDH

data hold time

tv(Q)

data output valid time

SPI slave

tDS

data set-up time

tDH

data hold time

tv(Q)

data output valid time

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