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PD035VX3 データシート(PDF) 7 Page - AZ Displays |
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PD035VX3 データシート(HTML) 7 Page - AZ Displays |
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7 / 27 page ![]() PD035VX3 The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page:7 Note 5-5: Typical Application Circuit V8 V5 OPEN V12 R2 1 2 1 2 1 2 1 2 1 2 V3 OPEN 1K OHM OPEN OPEN VDD2 1 2 R1 . C2 0. 1 uF C1 0.1 uF C3 C5 C7 0. 1 uF C6 0. 1 uF C4 0. 1 uF V10 1 2 R7 1.2K R3 R4 R5 R6 1.2K OHM V7 0.1uF 0.1uF Note 5-6: When OE is connected to high “1”, the driver outputs are disabled (Gate output = VEE). Under this condition, the operation of registers will not be affected. Note 5-7: Select up or down shift U/D STVU STVD Shift 1 Hi-Z Input Down to Up 0 Input Hi-Z Up to Down Note 5-8: Gate driver shift clock Note 5-9: Gate on voltage, VGG= +17V. Note 5-10: Gate off voltage, VEE= -10V. Note 5-11: ILED TYP.=20mA. |
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