XRT79L71 datasheet(21/441 Pages) EXAR

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PRELIMINARY

XRT79L71

1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

REV. P1.0.3

B10

TxFrame

Transmit End of DS3/E3 Frame Indicator:

This output pin is pulse "High" for one DS3 or E3 clock period, when the Transmit

Section of the XRT79L71 is processing the last bit of a given DS3 or E3 frame.

The implications of this output pin, for each mode of operation, are described

below.

ATM UNI/PPP/High-Speed HDLC Controller Mode:

This output pin serves as an end-of-frame indication to the local terminal equip-

ment.

Clear-Channel Framer Mode:

If the XRT79L71 is configured to operate in the Clear-Channel Framer mode,

then this output pin serves to alert the Local Terminal Equipment that it needs to

begin transmission of a new DS3 or E3 frame. Hence, the Local Terminal Equip-

ment uses this output signal to maintain Framing Alignment with the XRT79L71.

A11

TxFrameRef

Transmit DS3/E3 Framer - Framing Alignment Input pin:

If the the Transmit Section of the XRT79L71 is configured to operate in the Local-

Timing/Frame-Slave Mode, then the Transmit DS3/E3 Framer block will use this

input signal as the Framing Reference.

When the XRT79L71 is configured to operate in this mode any rising edge at this

input pin will cause the Transmit DS3/E3 Framer block to begin its creation of a

new DS3 or E3 frame. Consequently, the user must supply a clock signal that is

equivalent to the DS3 or E3 frame rates to this input pin. Further, it is imperative

that this clock signal be synchronized with the 44.736MHz or 34.368MHz clock

signal applied to the TxInClk input pin.

NOTE: This input pin should be tied to GND if it is not to be used as the Transmit

DS3/E3 Framer - Framing Reference input signal.

C10

TxInClk

Transmit DS3/E3 Framer Block - Timing Reference Signal:

If the Transmit Section of the XRT79L71 is configured to operate in the Local-

Timing Mode, then it will use this signal as the Timing Reference. If the

XRT79L71 is being operating in the DS3 Mode, then the user is expected to

apply a high-quality 44.736MHz clock signal to this input pin. Likewise, if the

XRT79L71 is being operated in the E3 Mode, then the user is expected to apply

a high-quality 34.368MHz clock signal to this input pin.

Note for Clear-Channel Framer Operation:

If the user is operating the XRT79L71 in the Clear-Channel Framer mode, then

the user should design the local terminal equipment circuitry, such that outbound

DS3 or E3 data will be output, upon the falling edge of TxInClk. The Transmit

Payload Data Input Interface within the Transmit Section of the XRT79L71 will

sample the data, applied to the TxSer input pin, upon the rising edge of TxInClk.

NOTE: This input pin should be tied to GND if the XRT79L71 is configured to

operate in the Loop-Timing Mode.

PIN #NAME

TYPE

DESCRIPTION

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