IS25LP032D-RGLA3:P datasheet(55/118 Pages) ISSI

部品番号	IS25LP032D-RGLA3:P

部品情報	SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PDF	118 Pages

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メーカー	ISSI [Integrated Silicon Solution, Inc]

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IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.13 CHIP ERASE OPERATION (CER, C7h/60h)

A Chip Erase (CER) instruction erases the entire memory array. Before the execution of CER instruction, the Write

Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is automatically reset after

completion of a chip erase operation.

The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,

otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase

voltage and timing.

Chip Erase (CER) instruction can be executed only when Block Protection (BP3~BP0) bits are set to 0s. If the BP

bits are not 0, the CER command is not executed and E_ERR and PROT_E are set.

Figure 8.20 Chip Erase Sequence In SPI Mode

Instruction = C7h/60h

CE#

SCK

Mode 3

Mode 0

High Impedance

Figure 8.21 Chip Erase Sequence In QPI Mode

C7h/60h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

IS25LP032D-RGLA3:P データシート(PDF) 55 Page - Integrated Silicon Solution, Inc