IS25LP016D-RGLA3:P datasheet(47/114 Pages) ISSI

部品番号	IS25LP016D-RGLA3:P

部品情報	SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PDF	114 Pages

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メーカー	ISSI [Integrated Silicon Solution, Inc]

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IS25LP016D

IS25WP016D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B10

03/09/2020

8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h)

A Block Erase (BER) instruction erases a 32/64Kbyte block. Before the execution of a BER instruction, the Write

Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the

completion of a block erase operation.

The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after the

CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic automatically

handles the erase voltage and timing.

Figure 8.16 Block Erase (64K) Sequence In SPI Mode

Instruction = D8h

CE #

SCK

3-byte Address

High Impedance

...

Mode 3

Mode 0

Figure 8.17 Block Erase (64K) Sequence In QPI Mode

D8h

CE#

SCK

IO[3:0]

3-byte Address

Mode 3

Mode 0

23:20 19:16 15:12 11:8

7:4

3:0

IS25LP016D-RGLA3:P データシート(PDF) 47 Page - Integrated Silicon Solution, Inc