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IS25LP064A-RHLA3 データシート(PDF) 47 Page - Integrated Silicon Solution, Inc

部品番号 IS25LP064A-RHLA3
部品情報  3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  99 Pages
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メーカー  ISSI [Integrated Silicon Solution, Inc]
ホームページ  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP064A-RHLA3 データシート(HTML) 47 Page - Integrated Silicon Solution, Inc

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IS25LP064A/032A
Integrated Silicon Solution, Inc.- www.issi.com
47
Rev. A
11/06/2015
8.15 WRITE DISABLE OPERATION (WRDI, 04h)
The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI
instruction is not required after the execution of a write instruction, since the WEL bit is automatically reset.
Figure 8.24 Write Disable Sequence
Instruction = 04h
CE#
SCK
SI
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SO
High Impedance
Figure 8.25 Write Disable QPI Sequence
04h
CE#
SCK
IO[3:0]
0
1
Mode 3
Mode 0



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