®

AS7C33512PFS18A

11/30/04; v.2.2

Alliance Semiconductor

17 of 20

AC test conditions

50

Ω

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+3.0V

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

for 3.3V I/O;

for 2.5V I/O

Notes:

1) For test conditions, see “AC Test Conditions”, Figures A, B, C

2) This parameter measured with output load condition in Figure C.

3) This parameter is sampled, but not 100% tested.

6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.

353

Ω / 1538Ω

5 pF*

319

Ω / 1667Ω

GND

Figure C: Output load (B)

*including scope

and jig capacitance

Thevenin equivalent:

+3.3V for 3.3V I/O;

/+2.5V for 2.5V I/O