June 2005

ASM2I9940L

rev 1.0

Low Voltage 1:18 Clock Distribution Chip

6 of 13

Notice: The information in this document is subject to change without notice.

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

Input HIGH Voltage

CMOS_CLK

2.4

V

Input LOW Voltage

CMOS_CLK

0.8

V

Peak–to–Peak Input

Voltage

PECL_CLK

500

1000

mV

Common Mode Range

PECL_CLK

V

Output HIGH Voltage

1.8

V

Output LOW Voltage

0.5

V

Input Current

±200

µA

Input Capacitance

4.0

pF

Power Dissipation Capacitance

10

pF

per output

Output Impedance

18

23

28

Ω

Maximum Quiescent Supply Current

0.5

1.0

mA

Symbol

Characteristic

Min

Typ Max

Unit

Condition

Maximum Input Frequency

200

MHz

Propagation Delay

PECL_CLK < 150MHz

CMOS_CLK < 150MHz

2.6

2.3

4.0

3.1

5.2

4.0

nS

Note

Propagation Delay

PECL_CLK > 150MHz

CMOS_CLK > 150MHz

2.8

2.3

3.8

3.1

5.0

4.0

nS

Output-to-output Skew

Within one bank

PECL_CLK

CMOS_CLK

200

200

pS

Note

Part–to–Part Skew

PECL_CLK < 150MHz

CMOS_CLK < 150MHz

2.6

1.7

nS

Notes

1,2

Part–to–Part Skew

PECL_CLK > 150MHz

CMOS_CLK > 150MHz

2.2

1.7

nS

Notes

1,2

Part–to–Part Skew

PECL_CLK

CMOS_CLK

1.2

1.0

nS

Notes

1,3

DC

Output Duty Cycle

45

40

50

50

55

60

%

%

Input DC = 50%

Input DC = 50%

Output Rise/Fall Time

0.3

1.2

nS

0.5 – 1.8 V

Note: 1. Tested using standard input levels, Production tested @ 150MHz.

2. Across temperature and voltage ranges, includes output skew.

3. For a specific temperature and voltage, includes output skew.