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STSPIN830 データシート(PDF) 19 Page - STMicroelectronics |
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STSPIN830 データシート(HTML) 19 Page - STMicroelectronics |
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19 / 27 page ![]() Figure 15. PCB layout example with single shunt (top layer) VREF capacitor for noise filtering: placed close to VREF leads STSPIN830 Ground plane: connects all the grounds on the TOP layer to reduce parasitic effects Vias on exposed pad to improve thermal dissipation Shunt resistor close to respective SENSE and SNS leads Ceramic bypass capacitor close to VS leads Several vias to connect the shunt ground with the bottom ground plane Several vias to connect the shunt tracks with the bottom plane Several vias to connect the shunt tracks with the bottom plane OUT tracks vias OUT tracks vias AM040391 Figure 16. PCB layout example with single shunt (bottom layer) STSPIN830 Top layer tracks Bottom layer tracks OUTs GND SENSE AM040392 STSPIN830 Layout recommendations DS12584 - Rev 2 page 19/27 |
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