MCP1633 datasheet(21/31 Pages) MICROCHIP

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DS20006289A-page 21

MCP1633

5.2

Recommended Startup Sequence

In order to reduce the startup stress, it is recommended

to use the sequence below (Figure 5-4). Depending of

the capacitor placed on the FSW pin, the necessary

delay for DIMM signal can be calculated with

Equation 2.

EQUATION 2:

NECESSARY TIME TO

REACH 90% OF THE FINAL

VALUE FOR VFSW

FIGURE 5-4:

Start-Up Sequence.

5.3

Layout Recommendations

Good printed circuit board layout techniques are

important to any switching circuitry and switching

power supplies are no different. Here are the guidelines

for the PCB layout:

• The exposed pad of MCP1633 QFN case is the

only connection to the internal device ground.

Connect this pad directly to the board ground

plane.

• Place at least four vias in the exposed pad land to

ensure good ground connection and remove heat

from the device.

• Use separate grounds for power and signal paths.

Keep high current paths away from sensitive

components and nodes (e.g. feedback and

compensation network components).

• Route the ISP and ISN together with Kelvin

connections to the current sense resistor with

traces as short as possible and use noise filters.

• Use short and strong connection between VEXT

and gate pin of the MOSFET.

• Locate the VREF, CSO, FSW, Comp, CSA gain

components near the MCP1633 case.

• Use separate connections to close each loop

directly to ground plane (VREF, CSO, FSW, Comp)

• Four-layer PCBs are highly recommended to

obtain optimum results regarding noise/EMI. Use

an internal layer as ground plane.

• Minimize the area of the high-current loops. Use

copper planes or large traces for high-current

connections in order to minimize the parasitic

inductances.

FIGURE 5-5:

Layout Example.



cnf

 rk



 2.3 10

–



VIN

DIMM

t(s)

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