W5100S datasheet(35/110 Pages) WIZNET

35 / 110 page

W5100S Datasheet Version1.2.5

35 / 110

R=W

Bit

Symbol

Description

WOL

Wake On LAN

To receive WOL Packet, PHYCR1[WOL] and MR2[WOL] must be set by

‘1’.

1 : Receive WOL Packet

0 : No Receive WOL Packet

Reserved

PWDN

PHY Power Down

1 : Enable Power Down Mode and SYS_CLK switching 25MHz

0 : Disable Power Down Mode and SYS_CLK selected by MR2[CLKSEL]

MR2[CLKSEL]

SYS_CLK

100 MHz

25 MHz

(Ref 7.4.1 Reset Timing)

[4:1]

Reserved

RST

PHY Reset

When PHY Reset Bit is set to ‘0’, SYS_CLK is switched to 25MHz. After

PHY Reset completed(PHYSR1[ACT]=‘1’), this Bit is automatically

cleared and SYS_CLK is turn back to the previous clock. (Ref 7.4.1

Reset Timing)

1 : PHY H/W Reset

0 : Normal

3.1.32 SLCR (SOCKET-less Command Register)

[RW] [0x004C] [0x00]

SLCR configures ARP and PING Request Transmission Command. Each Command must not be

executed at the same time and not configured before SLCR cleared. The results of each

Command is shown via SLIR (SOCKET-less Interrupt Register)

ARP

PING

W5100S データシート(PDF) 35 Page - WIZnet Co., Ltd

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