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IN74ACT112D データシート(PDF) 4 Page - Integral Corp.

部品番号 IN74ACT112D
部品情報  DUAL J-K FLIP-FLOP WITH SET AND RESET
PDF  5 Pages
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メーカー  INTEGRAL [Integral Corp.]
ホームページ  http://www.iksemi.com/
Logo INTEGRAL - Integral Corp.

IN74ACT112D データシート(HTML) 4 Page - Integral Corp.

  IN74ACT112D Datasheet HTML 1Page - Integral Corp. IN74ACT112D Datasheet HTML 2Page - Integral Corp. IN74ACT112D Datasheet HTML 3Page - Integral Corp. IN74ACT112D Datasheet HTML 4Page - Integral Corp. IN74ACT112D Datasheet HTML 5Page - Integral Corp.  
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IN74ACT112
4
AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25
°C
-40
°C to
85
°C
Unit
Min
Max
Min
Max
fmax
Maximum Clock Frequency (Figure 1)
145
125
MHz
tPLH
Propagation Delay, Clock to
Q or Q
(Figure 1)
1.0
14.0
1.0
15.0
ns
tPHL
Propagation Delay, Clock to
Q or Q
(Figure 1)
1.0
14.0
1.0
14.5
ns
tPLH
Propagation Delay, Set or Reset to
Q or
Q
(Figure 2)
1.0
12.0
1.0
12.5
ns
tPHL
Propagation Delay, Set or Reset to
Q or
Q
(Figure 2)
1.0
12.5
1.0
13.0
ns
CIN
Maximum Input Capacitance
4.5
4.5
pF
Typical @25
°C,VCC=5.0
V
CPD
Power Dissipation Capacitance
35
pF
TIMING REQUIREMENTS(VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25
°C
-40
°C to
85
°C
Unit
tsu
Minimum Setup Time, J or K to Clock
(Figure 3)
2.0
2.5
ns
th
Minimum Hold Time, Clock to J or K
(Figure 3)
2.0
2.0
ns
tw
Minimum Pulse Width, Clock (Figure 1)
5.0
6.0
ns
tw
Minimum Pulse Width,Set or Reset (Figure
2)
5.5
6.0
ns
trec
Minimum Recovery Time, Set or Reset to
Clock (Figure 2)
0
0
ns



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