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STM32F091CBH6TP データシート(PDF) 90 Page - STMicroelectronics |
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STM32F091CBH6TP データシート(HTML) 90 Page - STMicroelectronics |
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90 / 128 page ![]() Electrical characteristics STM32F091xB STM32F091xC 90/128 DocID026284 Rev 4 Gain error(3) Gain error - - ±0.5 % Given for the DAC in 12-bit configuration tSETTLING(3) Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±1LSB -3 4 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Update rate(3) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) -- 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ tWAKEUP(3) Wakeup time from off state (Setting the ENx bit in the DAC Control register) -6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement - –67 –40 dB No RLOAD, CLOAD = 50 pF 1. Guaranteed by design, not tested in production. 2. The DAC is in “quiescent mode” when it keeps the value steady on the output so no dynamic consumption is involved. 3. Data based on characterization results, not tested in production. Table 60. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments |
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