データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

STM32H747AI データシート(PDF) 186 Page - STMicroelectronics

部品番号 STM32H747AI
部品情報  Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
PDF  252 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H747AI データシート(HTML) 186 Page - STMicroelectronics

Back Button STM32H747AI Datasheet HTML 182Page - STMicroelectronics STM32H747AI Datasheet HTML 183Page - STMicroelectronics STM32H747AI Datasheet HTML 184Page - STMicroelectronics STM32H747AI Datasheet HTML 185Page - STMicroelectronics STM32H747AI Datasheet HTML 186Page - STMicroelectronics STM32H747AI Datasheet HTML 187Page - STMicroelectronics STM32H747AI Datasheet HTML 188Page - STMicroelectronics STM32H747AI Datasheet HTML 189Page - STMicroelectronics STM32H747AI Datasheet HTML 190Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 186 / 252 page
background image
Electrical characteristics
STM32H747xI/G
176/242
DS12930 Rev 1
The following table summarizes the parameters measured in DDR mode.
tw(CKH)
QUADSPI clock high
and low time Even
division
PRESCALER[7:0] =
n = 0,1,3,5...
TCK/2–0.5
-
TCK/2
ns
tw(CKL)
TCK/2
-
TCK/2+0.5
tw(CKH)
QUADSPI clock high
and low time Odd
division
PRESCALER[7:0] =
n = 2,4,6,8...
(n/2)*TCK/(n+1)-0.5
-
(n/2)*TCK/ (n+1)
tw(CKL)
(n/2+1)*TCK/(n+1)
-
(n/2+1)*TCK/
(n+1)+0.5
ts(IN)
Data input setup time
-
1-
-
th(IN)
Data input hold time
3.5
-
-
tv(OUT)
Data output valid time
-
-
1
2
th(OUT)
Data output hold time
-
0
-
-
1. Guaranteed by characterization results.
Table 95. QUADSPI characteristics in SDR mode(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 96. QUADSPI characteristics in DDR mode(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fck11/TCK
QUADSPI clock frequency
2.7<VDD<3.6 V
CL = 20 pF
--
100
MHz
1.62<VDD<3.6 V
CL = 15 pF
--
100
tw(CKH)
QUADSPI clock high and
low time Even division
PRESCALER[7:0] =
n = 0,1,3,5...
TCK/2–0.5
-
TCK/2
ns
tw(CKL)
TCK/2
-
TCK/2+0.5
tw(CKH)
QUADSPI clock high and
low time Odd division
PRESCALER[7:0] =
n = 2,4,6,8...
(n/2)*TCK/
(n+1)-0.5
-
(n/2)*TCK/
(n+1)
tw(CKL)
(n/2+1)*TCK/
(n+1)
-
(n/2+1)*TCK /
(n+1)+0.5
tsr(IN), tsf(IN)
Data input setup time
-
1.5
-
-
thr(IN),thf(IN)
Data input hold time
-
3.5
-
-
tvr(OUT),
tvf(OUT)
Data output valid time
DHHC=0
-
5
6
DHHC=1
PRESCALER[7:0] =
1,2…
-TCK/4+1
TCK/4+2
thr(OUT),
thf(OUT)
Data output hold time
DHHC=0
3
-
-
DHHC=1
PRESCALER[7:0]=1
,2…
TCK/4
-
-
1. Guaranteed by characterization results.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com