データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

STM32L552CC データシート(PDF) 60 Page - STMicroelectronics

部品番号 STM32L552CC
部品情報  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 165 DMIPS, up to 512 KB Flash memory, 256 KB SRAM, SMPS
PDF  340 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L552CC データシート(HTML) 60 Page - STMicroelectronics

Back Button STM32L552CC_V01 Datasheet HTML 56Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 57Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 58Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 59Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 60Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 61Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 62Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 63Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 64Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 60 / 340 page
background image
Functional overview
STM32L552xx
60/340
DS12737 Rev 6
•
Three functional modes: indirect, status-polling, and memory-mapped
•
Read and write support in memory-mapped mode
•
Supports for single, dual, quad and octal communication
•
Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two
quad memories in parallel.
•
SDR and DTR support
•
Data strobe support
•
Fully programmable opcode for both indirect and memory mapped mode
•
Fully programmable frame format for both indirect and memory mapped mode
•
Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
–
Instruction phase
–
Address phase
–
Alternate bytes phase
–
Dummy cycles phase
–
Data phase
•
HyperBusTM support
•
Integrated FIFO for reception and transmission
•
8, 16, and 32-bit data accesses are allowed
•
DMA channel for indirect mode operations
•
Timeout management
•
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
TrustZone security
When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two non-secure area can be configured thought the TZSC MPCWM1 controller with a
granularity of 64 Kbytes.
The OCTOSPI registers can be configured as secure through the TZSC controller.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com