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STM32G474PBY3TR データシート(PDF) 174 Page - STMicroelectronics

部品番号 STM32G474PBY3TR
部品情報  Arm® Cortex®-M4 32-bit MCUFPU, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math acc, 184 ps 12 chan Hi-res timer
PDF  236 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G474PBY3TR データシート(HTML) 174 Page - STMicroelectronics

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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
174/236
DS12288 Rev 5
Figure 35. SPI timing diagram - slave mode and CPHA = 0
tv(SO)
Data output valid time
Slave mode
2.7 V < VDD < 3.6 V
Voltage Range V1
-9
12
ns
Slave mode
1.71 V < VDD < 3.6 V
Voltage Range V1
-9
18
Slave mode
1.71 V < VDD < 3.6 V
Voltage Range V2
-13
22
tv(MO)
Master mode
-
3.5
4.5
th(SO)
Data output hold time
Slave mode 1.71 V < VDD < 3.6 V
6
-
-
Slave mode Range V2
9
-
-
th(MO)
Master mode
2
-
-
1. Guaranteed by characterization results.
2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into
SCK low or high-phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
Table 89. SPI characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max(2)
Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO)
tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT
Next bits OUT
th(SO)
tf(SCK)
Last bit IN



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