データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

STM32G474PBY3TR データシート(PDF) 181 Page - STMicroelectronics

部品番号 STM32G474PBY3TR
部品情報  Arm® Cortex®-M4 32-bit MCUFPU, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math acc, 184 ps 12 chan Hi-res timer
PDF  236 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G474PBY3TR データシート(HTML) 181 Page - STMicroelectronics

Back Button STM32G474PBY3TR Datasheet HTML 177Page - STMicroelectronics STM32G474PBY3TR Datasheet HTML 178Page - STMicroelectronics STM32G474PBY3TR Datasheet HTML 179Page - STMicroelectronics STM32G474PBY3TR Datasheet HTML 180Page - STMicroelectronics STM32G474PBY3TR Datasheet HTML 181Page - STMicroelectronics STM32G474PBY3TR Datasheet HTML 182Page - STMicroelectronics STM32G474PBY3TR Datasheet HTML 183Page - STMicroelectronics STM32G474PBY3TR Datasheet HTML 184Page - STMicroelectronics STM32G474PBY3TR Datasheet HTML 185Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 181 / 236 page
background image
DS12288 Rev 5
181/236
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
200
5.3.28
FSMC characteristics
Unless otherwise specified, the parameters given in Table 94 to Table 107 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 17, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 x VDD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 40 through Figure 43 represent asynchronous waveforms and Table 94 through
Table 101 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
AddressSetupTime = 0x1
•
AddressHoldTime = 0x1
•
DataHoldTime = 0x1
•
ByteLaneSetup = 0x1
•
DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
•
BusTurnAroundDuration = 0x0
In all timing tables, the THCLK is the HCLK clock period.
tv(TX)
Data output valid time
Master mode
-
0.5
1.5
ns
Slave mode
-
10
22
th(RX)
Data output hold time
Master mode
0
-
-
Slave mode
7
-
-
1. Based on characterization, not tested in production.
Table 93. USART electrical characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com