© 2016 Integrated Device Technology, Inc

5

November 14, 2016

ZSC31015 Datasheet

List of Figures

Figure 2.1

ZSC31015 Block Diagram ..................................................................................................................13

Figure 2.2

DAC Output Timing for Highest Update Rate.....................................................................................18

Figure 3.1

General Working Mode.......................................................................................................................24

Figure 3.2

Manchester Duty Cycle.......................................................................................................................25

Figure 3.3

19-Bit Write Frame..............................................................................................................................26

Figure 3.4

Read Acknowledge.............................................................................................................................26

Figure 3.5

Digital Output (NOM) Bridge Readings ..............................................................................................27

Figure 3.6

Digital Output (NOM) Bridge Readings with Temperature .................................................................27

Figure 3.7

Read EEPROM Contents ...................................................................................................................28

Figure 3.8

Transmission of a Number of Data Packets .......................................................................................28

Figure 3.9

ZACwire™ Output Timing for Lower Update Rates............................................................................29

Figure 4.1

Rail-to-Rail Ratiometric Voltage Output

– Temperature Compensation via External Diode ..............42

Figure 4.2

Absolute Analog Voltage Output

– Temperature Compensation via Internal Temperature PTAT with

External JFET Regulation...................................................................................................................43

Figure 4.3

Ratiometric Output, Temperature Compensation via Internal Diode..................................................44

Figure 5.1

EEPROM Validation and Restoration Procedure ...............................................................................46

Figure 6.1

ZSC31015 Pin-Out Diagram...............................................................................................................47