LT8604 datasheet(16/20 Pages) AD

16 / 20 page

LT8604

Rev. 0

For more information www.analog.com

EN/UV

TR/SS

GND

VIAS

GND

CPL

LT8604

VIN

BIAS

INTVCC

BST

VOUT

CINTVCC

CBST

COUT

CIN

GND

VOUT

8604 F04

PCB Layout

For proper operation and minimum EMI, care must be

taken during printed circuit board layout. Figure 4 shows

the recommended component placement with trace,

ground plane and via locations. Note that large, switched

currents flow in the LT8604’s VIN pins, GND pins, and the

input capacitor (CIN). The loop formed by the input capaci-

tor should be as small as possible by placing the capacitor

adjacent to the VIN and GND pins. When using a physically

large input capacitor the resulting loop may become too

large in which case using a small case/value capacitor

placed close to the VIN and GND pins plus a larger capaci-

tor further away is preferred. These components, along

with the inductor and output capacitor, should be placed

on the same side of the circuit board, and their connec-

tions should be made on that layer. Place a local, unbroken

ground plane under the application circuit on the layer

closest to the surface layer. The SW and BOOST nodes

should be as small as possible. Finally, keep the FB and

RT nodes small so that the ground traces will shield them

from the SW and BOOST nodes. The exposed pad on the

bottom of the package must be soldered to ground so that

the pad is connected to ground electrically and also acts

as a heat sink thermally. To keep thermal resistance low,

extend the ground plane as much as possible, and add

thermal vias near the LT8604 to additional ground planes

within the circuit board and on the bottom side.

Figure 4 shows the basic guidelines for a layout example.

Figure 4. Recommended PCB Layout (Not to Scale)

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