GC5316 datasheet(52/75 Pages) TI

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GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

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imask_rx_pmeter_lsb

Interrupt mask bits for the receive composite power

meter− 8 LSBs

imask_tx_cic

Interrupt mask bits for overflow detection in the transmit

cics

5.1.5 General Receive Controls

These registers control the receive interface to the DDC channels

VARIABLE NAME

TYPE

PAGE

ADDRESS

LSB

POSITION

BIT

WIDTH

DEFAULT

DESCRIPTION

ddc_counter_lsb

1800

65535

32-bit interval timer common to all DDC sync

inputs. This timer may be programmed to any

interval count, and each DDC synchronization

input can select this counter as a source. This

counter increments on each RX clock rising

edge. 16 LSBs

ddc_counter_msb

1800

65535

32-bit interval timer common to all DDC sync

inputs.16 MSBs

ssel_ddc_counter

1800

Selects the sync source for the DDC sync

counter.

ddc_counter_width

1800

Sets the width of the counter generated sync

pulse in RX clock cycles, from 1 to 256. The

width of the the ddc_counter pulse should be set

wide enough to be asserted for an entire clock

period of the slowest block to use this sync

ssel_adc_fifo

1800

Selects the sync source for the adc FIFO block.

Sync reinitializes the read and write pointers of

the FIFO.

ssel_resamp

1800

Selects the sync source for the

ADC_RESAMPLER block.

ssel_rxsync_out

1800

Selects the sync source for the RXSYNC_OUT

pin.

ssel_rxin

1800

Synchronizes the rx_distribution bus source and

destination and clock generation in each of the

DDC blocks.

rate_sel

1800

This selects the FIFO output rate when

adc_fifo_bypass = 0. When using the resampler,

this value should be programmed to a 0. When

set to 0, the FIFO output is clocked by rxclk

(gated if resampler is on and decimating by 1.5).

When set to 1, the FIFO output rate is 1/2 of

rxclk rate. When set to 2, the FIFO output rate is

1/4 of rxclk rate, and when set to 3, the FIFO

output is at 1/8 of rxclk rate. E.g.: With rxclk

122.88 MHz, set rate_sel to 0, 1, 2 or 3

respectively for adcclk 122.88, 61.44, 30.72 or

15.36 MHz.

resampler_ena

1800

When asserted turns on the ADC_RESAMPLER

block.

adc_fifo_bypass

1800

When asserted, the adc_fifo is bypassed. Input

data is then clocked in directly using the RXCLK

input. The ssel_rxin selection value will control

the location of the internally generated sample

clock when this bit is asserted.

resampler_decim

1800

This tells the ADC_RESAMPLER block the

decimation factor (1=1.5X, 0=2X)

nz_pwr_mask

1820

Used along with rduz_sens_ena, it selects the

noise bits to be added to the ADC input sample

when asserted.

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