MC56F81663VLC datasheet(46/73 Pages) NXP

46 / 73 page

Table 12. Current Consumption (Unit: mA) (continued)

Mode

Maximum

Frequency

Conditions

Typical at

3.3 V,

25°C

Maximum

at 3.6 V,

105°C

Maximum

at 3.6V,

125°C

IDD1 IDDA IDD1 IDDA IDD1 IDDA

• PLL disabled

• Repeat NOP instructions

• All peripheral modules, except COP and EWM,

disabled and clocks gated off

• Simple loop running from platform instruction buffer

VLPWAIT

200 kHz

• 32 kHz Device Clock

• Clocked by a 64 kHz external clock source

• Oscillator in power down

• All ROSCs disabled

• Large regulator is in standby

• Small regulator is disabled

• PLL disabled

• All peripheral modules, except COP, disabled and

clocks gated off

• Processor core in wait mode

0.4

—

7.5

—

9.0

—

VLPSTOP

200 kHz

• 32 kHz Device Clock

• Clocked by a 64 kHz external clock source

• Oscillator in power down

• All ROSCs disabled

• Large regulator is in standby.

• Small regulator is disabled.

• PLL disabled

• All peripheral modules, except COP, disabled and

clocks gated off

• Processor core in stop mode

0.4

—

7.5

—

9.0

—

1. No output switching, all ports configured as inputs, all inputs low, no DC loads.

2. In all chip LP modes and flash memory VLP modes, the maximum frequency for flash memory operation is 500 kHz due to

the fixed frequency ratio of 1:2 between the CPU clock and the flash clock when running with 2 MHz external clock input

and CPU running at 1 MHz.

10.3.6 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.nxp.com.

2. Perform a keyword search for “EMC design.”

General

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

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