MC56F81663 datasheet(62/73 Pages) NXP

部品番号	MC56F81663

部品情報	DSC based on 32-bit 56800EX core

PDF	73 Pages

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メーカー	NXP [NXP Semiconductors]

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11.6.3 QDC Timing Specifications

Parameters listed are guaranteed by design.

Table 34. Quadrature Decoder Timing

Characteristic

Symbol

Min1

Max

Unit

Quadrature input period

4T + 12

—

Quadrature input high/low period

PHL

2T + 6

—

Quadrature phase period

PPH

1T + 3

—

1. In the formulas listed, T equals the system clock cycle. For 50 MHz operation, T = 20 ns. For 100 MHz operation,

T = 10 ns.

Phase A

Input

PPH

PHL

Input

Phase B

PPH

PHL

Input period

Phase period

Input high/low period

Figure 15. Quadrature Decoder Timing

11.7 Communication interfaces

11.7.1 Queued Serial Peripheral Interface (SPI) timing

Parameters listed are guaranteed by design.

Table 35. SPI timing

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time

—

Figure 16

Table continues on the next page...

PWMs and timers

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

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