PSD813F1V-70MIT datasheet(96/110 Pages) STMICROELECTRONICS

96 / 110 page

PSD813F1V

96/110

Figure 50. Peripheral I/O WRITE Timing

Table 65. Port A Peripheral Data Mode WRITE Timing (5V devices)

Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).

2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.

3. Any input used to select Port A Data Peripheral mode.

4. Data is already stable on Port A.

5. Data stable on ADIO pins to data on Port A.

Table 66. Port A Peripheral Data Mode WRITE Timing (3V devices)

Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode) signals.

2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.

3. Any input used to select Port A Data Peripheral mode.

4. Data is already stable on Port A.

5. Data stable on ADIO pins to data on Port A.

Symbol

Parameter

Conditions

-90

-12

-15

Unit

Min

Max

Min

Max

Min

Max

tWLQV–PA

WR to Data Propagation Delay

(Note 2)

tDVQV–PA

Data to Port A Data Propagation Delay

(Note 5)

tWHQZ–PA

WR Invalid to Port A Tri-state

(Note 2)

Symbol

Parameter

Conditions

-15

-20

Unit

Min

Max

Min

Max

tWLQV–PA

WR to Data Propagation Delay

(Note 2)

tDVQV–PA

Data to Port A Data Propagation Delay

(Note 5)

tWHQZ–PA

WR Invalid to Port A Tri-state

(Note 2)

tDVQV (PA)

tWLQV

(PA)

tWHQZ (PA)

ADDRESS

DATA OUT

A / D BUS

PORT A

DATA OUT

ALE /AS

AI02898

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